1. Field of Invention
This invention relates to a logic gate, and more particularly to improved high speed emitter coupled logic (ECL) gate.
2. Description of the Prior Art
Many prior art ECL gates are data bit rate limited to somewhere around 250 megabits per second. These rates are unacceptable in high speed communication applications, for example in certain pulse code modulating environments. One attempt to increase the speed of ECL gates is directed towards varying circuit impedances in order to reduce current swings in the emitter-follower output transistor during switching. Another situation increases power dissipation and moreover speed improvement is practically limited by design considerations. Another approach is to employ sophisticated processing and device techniques which essentially minimizes collect-to-substrate capacitance in order to improve rise and fall times of the generated signal. In addition to being costly and more difficult to control these approaches are also performance limited when it is desirous to improve the data bit rate by an order of magnitude over that now obtainable with known prior art ECL gates. For example, certain applications require a 600 megabit per second data rate.
It is therefore an object of the invention to provide an improved high speed, high band width ECL gate capable of operating in the 600 megabit per second data range.
Another object of the present invention is to provide an improved ECL gate wherein AC beta roll off is minimized, thus significantly improving rise and fall times, and cross talk also is reduced.
Another object of the present invention is to provide an improved ECL gate capable of operating at significantly higher data bit rates without corresponding output signal attenuation.
In accordance with the aforementioned objects, the present invention provides an ECL logic gate wherein switchable current sinks connected to the emitter terminal of the emitter-follower output transistor maintain a substantially constant current flow through the emitter-follower output transistor during switching of the logic gate.